module count_clk(
  input          clock,
  input          reset,
  output         io_Data_in,
  output [9:0]   io_count_clk_in,
  output [9:0]   io_count_clk_delay,
  output [9:0]   io_count_clk_enable,
  output [9:0]   io_count_clk_out,
  input  [209:0] io_Data,
  input  [2:0]   io_stateReg
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
`endif // RANDOMIZE_REG_INIT
  reg [9:0] count_clk_in; // @[PUF_Core.scala 145:36]
  reg [9:0] count_clk_delay; // @[PUF_Core.scala 146:36]
  reg [9:0] count_clk_enable; // @[PUF_Core.scala 147:36]
  reg [9:0] count_clk_out; // @[PUF_Core.scala 148:36]
  wire [209:0] _the_data_in_T = io_Data >> count_clk_in; // @[PUF_Core.scala 151:35]
  wire [9:0] _count_clk_in_T_1 = count_clk_in + 10'h1; // @[PUF_Core.scala 156:42]
  wire [9:0] _count_clk_delay_T_1 = count_clk_delay + 10'h1; // @[PUF_Core.scala 162:45]
  wire [9:0] _count_clk_enable_T_1 = count_clk_enable + 10'h1; // @[PUF_Core.scala 169:50]
  wire [9:0] _count_clk_out_T_1 = count_clk_out + 10'h1; // @[PUF_Core.scala 176:43]
  assign io_Data_in = _the_data_in_T[0]; // @[PUF_Core.scala 151:52]
  assign io_count_clk_in = count_clk_in; // @[PUF_Core.scala 183:25]
  assign io_count_clk_delay = count_clk_delay; // @[PUF_Core.scala 184:25]
  assign io_count_clk_enable = count_clk_enable; // @[PUF_Core.scala 185:25]
  assign io_count_clk_out = count_clk_out; // @[PUF_Core.scala 186:25]
  always @(posedge clock) begin
    if (reset) begin // @[PUF_Core.scala 145:36]
      count_clk_in <= 10'h0; // @[PUF_Core.scala 145:36]
    end else if (io_stateReg == 3'h1) begin // @[PUF_Core.scala 155:36]
      count_clk_in <= _count_clk_in_T_1; // @[PUF_Core.scala 156:25]
    end else begin
      count_clk_in <= 10'h0; // @[PUF_Core.scala 158:25]
    end
    if (reset) begin // @[PUF_Core.scala 146:36]
      count_clk_delay <= 10'h0; // @[PUF_Core.scala 146:36]
    end else if (io_stateReg == 3'h2) begin // @[PUF_Core.scala 161:36]
      count_clk_delay <= _count_clk_delay_T_1; // @[PUF_Core.scala 162:25]
    end else begin
      count_clk_delay <= 10'h0; // @[PUF_Core.scala 165:25]
    end
    if (reset) begin // @[PUF_Core.scala 147:36]
      count_clk_enable <= 10'h0; // @[PUF_Core.scala 147:36]
    end else if (io_stateReg == 3'h3) begin // @[PUF_Core.scala 168:37]
      count_clk_enable <= _count_clk_enable_T_1; // @[PUF_Core.scala 169:29]
    end else begin
      count_clk_enable <= 10'h0; // @[PUF_Core.scala 172:29]
    end
    if (reset) begin // @[PUF_Core.scala 148:36]
      count_clk_out <= 10'h0; // @[PUF_Core.scala 148:36]
    end else if (io_stateReg == 3'h4) begin // @[PUF_Core.scala 175:37]
      count_clk_out <= _count_clk_out_T_1; // @[PUF_Core.scala 176:25]
    end else begin
      count_clk_out <= 10'h0; // @[PUF_Core.scala 179:25]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  count_clk_in = _RAND_0[9:0];
  _RAND_1 = {1{`RANDOM}};
  count_clk_delay = _RAND_1[9:0];
  _RAND_2 = {1{`RANDOM}};
  count_clk_enable = _RAND_2[9:0];
  _RAND_3 = {1{`RANDOM}};
  count_clk_out = _RAND_3[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module puf_core(
  input          clock,
  input          reset,
  output         io_out_Data_in,
  output         io_out_Ena_in,
  output         io_out_Clk_in,
  output         io_out_Ena_out,
  output         io_out_Clk_out,
  input          io_ctr_puf_in_valid,
  output         io_ctr_puf_in_ready,
  input  [209:0] io_ctr_puf_data_in,
  output         io_ctr_puf_out_valid,
  input          io_clk_Clk
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
  wire  M_Count_Clk_clock; // @[PUF_Core.scala 39:39]
  wire  M_Count_Clk_reset; // @[PUF_Core.scala 39:39]
  wire  M_Count_Clk_io_Data_in; // @[PUF_Core.scala 39:39]
  wire [9:0] M_Count_Clk_io_count_clk_in; // @[PUF_Core.scala 39:39]
  wire [9:0] M_Count_Clk_io_count_clk_delay; // @[PUF_Core.scala 39:39]
  wire [9:0] M_Count_Clk_io_count_clk_enable; // @[PUF_Core.scala 39:39]
  wire [9:0] M_Count_Clk_io_count_clk_out; // @[PUF_Core.scala 39:39]
  wire [209:0] M_Count_Clk_io_Data; // @[PUF_Core.scala 39:39]
  wire [2:0] M_Count_Clk_io_stateReg; // @[PUF_Core.scala 39:39]
  reg  the_ena_out; // @[PUF_Core.scala 19:32]
  reg [2:0] stateReg; // @[PUF_Core.scala 37:40]
  reg  io_out_Ena_out_REG; // @[PUF_Core.scala 45:36]
  wire  _T = stateReg == 3'h1; // @[PUF_Core.scala 73:20]
  wire  _T_1 = stateReg == 3'h2; // @[PUF_Core.scala 79:25]
  wire  _T_2 = stateReg == 3'h3; // @[PUF_Core.scala 85:25]
  wire  _T_3 = stateReg == 3'h4; // @[PUF_Core.scala 91:25]
  wire  _GEN_3 = stateReg == 3'h3 | _T_3; // @[PUF_Core.scala 85:39 PUF_Core.scala 87:25]
  wire  _GEN_6 = stateReg == 3'h2 ? 1'h0 : _GEN_3; // @[PUF_Core.scala 79:38 PUF_Core.scala 81:25]
  wire  the_clk_out = stateReg == 3'h1 ? 1'h0 : _GEN_6; // @[PUF_Core.scala 73:33 PUF_Core.scala 75:25]
  wire [9:0] count_clk_out = M_Count_Clk_io_count_clk_out;
  wire [7:0] _trigger_idle_T_1 = 8'h80 - 8'h2; // @[PUF_Core.scala 70:65]
  wire [9:0] _GEN_20 = {{2'd0}, _trigger_idle_T_1}; // @[PUF_Core.scala 70:49]
  wire  trigger_idle = count_clk_out == _GEN_20; // @[PUF_Core.scala 70:49]
  wire [9:0] count_clk_in = M_Count_Clk_io_count_clk_in;
  wire  trigger_delay = count_clk_in == 10'hd2; // @[PUF_Core.scala 67:49]
  wire [9:0] count_clk_delay = M_Count_Clk_io_count_clk_delay;
  wire  trigger_enable = count_clk_delay == 10'h4; // @[PUF_Core.scala 68:49]
  wire [9:0] count_clk_enable = M_Count_Clk_io_count_clk_enable;
  wire  trigger_output = count_clk_enable == 10'h2; // @[PUF_Core.scala 69:49]
  wire  _GEN_4 = stateReg == 3'h3 ? 1'h0 : _T_3; // @[PUF_Core.scala 85:39 PUF_Core.scala 88:25]
  wire  _GEN_5 = stateReg == 3'h2 | _T_2; // @[PUF_Core.scala 79:38 PUF_Core.scala 80:25]
  wire  _GEN_7 = stateReg == 3'h2 ? 1'h0 : _GEN_4; // @[PUF_Core.scala 79:38 PUF_Core.scala 82:25]
  wire [2:0] _GEN_13 = trigger_output ? 3'h4 : stateReg; // @[PUF_Core.scala 116:32 PUF_Core.scala 117:25 PUF_Core.scala 37:40]
  wire [2:0] _GEN_14 = trigger_idle ? 3'h0 : stateReg; // @[PUF_Core.scala 121:30 PUF_Core.scala 122:25 PUF_Core.scala 37:40]
  wire [2:0] _GEN_15 = io_ctr_puf_in_valid ? 3'h1 : stateReg; // @[PUF_Core.scala 126:31 PUF_Core.scala 127:25 PUF_Core.scala 37:40]
  wire [2:0] _GEN_16 = _T_3 ? _GEN_14 : _GEN_15; // @[PUF_Core.scala 120:38]
  count_clk M_Count_Clk ( // @[PUF_Core.scala 39:39]
    .clock(M_Count_Clk_clock),
    .reset(M_Count_Clk_reset),
    .io_Data_in(M_Count_Clk_io_Data_in),
    .io_count_clk_in(M_Count_Clk_io_count_clk_in),
    .io_count_clk_delay(M_Count_Clk_io_count_clk_delay),
    .io_count_clk_enable(M_Count_Clk_io_count_clk_enable),
    .io_count_clk_out(M_Count_Clk_io_count_clk_out),
    .io_Data(M_Count_Clk_io_Data),
    .io_stateReg(M_Count_Clk_io_stateReg)
  );
  assign io_out_Data_in = M_Count_Clk_io_Data_in; // @[PUF_Core.scala 22:33 PUF_Core.scala 56:29]
  assign io_out_Ena_in = stateReg == 3'h1 ? 1'h0 : _GEN_5; // @[PUF_Core.scala 73:33 PUF_Core.scala 74:25]
  assign io_out_Clk_in = stateReg == 3'h1 | _GEN_7; // @[PUF_Core.scala 73:33 PUF_Core.scala 76:25]
  assign io_out_Ena_out = io_out_Ena_out_REG; // @[PUF_Core.scala 45:25]
  assign io_out_Clk_out = stateReg == 3'h1 ? 1'h0 : _GEN_6; // @[PUF_Core.scala 73:33 PUF_Core.scala 75:25]
  assign io_ctr_puf_in_ready = count_clk_in == 10'hd2; // @[PUF_Core.scala 67:49]
  assign io_ctr_puf_out_valid = trigger_idle & ~the_clk_out; // @[PUF_Core.scala 63:46]
  assign M_Count_Clk_clock = io_clk_Clk; // @[PUF_Core.scala 49:29]
  assign M_Count_Clk_reset = reset;
  assign M_Count_Clk_io_Data = io_ctr_puf_data_in; // @[PUF_Core.scala 50:29]
  assign M_Count_Clk_io_stateReg = stateReg; // @[PUF_Core.scala 51:29]
  always @(posedge clock) begin
    if (stateReg == 3'h1) begin // @[PUF_Core.scala 73:33]
      the_ena_out <= 1'h0; // @[PUF_Core.scala 75:25]
    end else if (stateReg == 3'h2) begin // @[PUF_Core.scala 79:38]
      the_ena_out <= 1'h0; // @[PUF_Core.scala 81:25]
    end else begin
      the_ena_out <= _GEN_3;
    end
    if (reset) begin // @[PUF_Core.scala 37:40]
      stateReg <= 3'h0; // @[PUF_Core.scala 37:40]
    end else if (_T) begin // @[PUF_Core.scala 105:33]
      if (trigger_delay) begin // @[PUF_Core.scala 106:31]
        stateReg <= 3'h2; // @[PUF_Core.scala 107:25]
      end
    end else if (_T_1) begin // @[PUF_Core.scala 110:38]
      if (trigger_enable) begin // @[PUF_Core.scala 111:31]
        stateReg <= 3'h3; // @[PUF_Core.scala 112:25]
      end
    end else if (_T_2) begin // @[PUF_Core.scala 115:38]
      stateReg <= _GEN_13;
    end else begin
      stateReg <= _GEN_16;
    end
    io_out_Ena_out_REG <= the_ena_out; // @[PUF_Core.scala 45:36]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  the_ena_out = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  stateReg = _RAND_1[2:0];
  _RAND_2 = {1{`RANDOM}};
  io_out_Ena_out_REG = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module read_data(
  input          clock,
  input          reset,
  input          io_ena,
  input          io_channel,
  output [127:0] io_output
);
`ifdef RANDOMIZE_REG_INIT
  reg [127:0] _RAND_0;
  reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
  reg [127:0] result; // @[PUF_Top.scala 90:32]
  reg [9:0] count; // @[PUF_Top.scala 91:32]
  wire [9:0] _count_T_1 = count + 10'h1; // @[PUF_Top.scala 94:35]
  wire [7:0] _T_1 = 8'h80 - 8'h1; // @[PUF_Top.scala 100:43]
  wire [9:0] _GEN_2 = {{2'd0}, _T_1}; // @[PUF_Top.scala 100:29]
  wire [126:0] result_lo = result[127:1]; // @[PUF_Top.scala 102:44]
  wire [127:0] _result_T = {io_channel,result_lo}; // @[Cat.scala 30:58]
  assign io_output = result; // @[PUF_Top.scala 105:21]
  always @(posedge clock) begin
    if (reset) begin // @[PUF_Top.scala 90:32]
      result <= 128'h0; // @[PUF_Top.scala 90:32]
    end else if (io_ena & count < _GEN_2) begin // @[PUF_Top.scala 100:51]
      result <= _result_T; // @[PUF_Top.scala 102:17]
    end
    if (reset) begin // @[PUF_Top.scala 91:32]
      count <= 10'h0; // @[PUF_Top.scala 91:32]
    end else if (io_ena) begin // @[PUF_Top.scala 93:19]
      count <= _count_T_1; // @[PUF_Top.scala 94:25]
    end else begin
      count <= 10'h0; // @[PUF_Top.scala 96:25]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {4{`RANDOM}};
  result = _RAND_0[127:0];
  _RAND_1 = {1{`RANDOM}};
  count = _RAND_1[9:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module Clk_Divider2(
  input   clock,
  input   reset,
  output  io_clk_out
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
  reg  the_clk; // @[Clk_Divider2.scala 12:28]
  assign io_clk_out = the_clk; // @[Clk_Divider2.scala 15:29]
  always @(posedge clock) begin
    if (reset) begin // @[Clk_Divider2.scala 12:28]
      the_clk <= 1'h0; // @[Clk_Divider2.scala 12:28]
    end else begin
      the_clk <= ~the_clk; // @[Clk_Divider2.scala 13:17]
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  the_clk = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module puf_subtop(
  input          clock,
  input          reset,
  output         io_out_Data_in,
  output         io_out_Ena_in,
  output         io_out_Clk_in,
  input          io_out_Data_out,
  output         io_out_Ena_out,
  output         io_out_Clk_out,
  output         io_out_Clk,
  output         io_out_WL_Enable,
  output         io_out_Write_Ena,
  input          io_ctr_puf_in_valid,
  output         io_ctr_puf_in_ready,
  input  [209:0] io_ctr_puf_data_in,
  output         io_ctr_puf_out_valid,
  output [127:0] io_ctr_puf_data_out,
  input          io_ctr_puf_wl_ena,
  input          io_ctr_puf_write_ena
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
`endif // RANDOMIZE_REG_INIT
  wire  M_PUF_Core_clock; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_reset; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_out_Data_in; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_out_Ena_in; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_out_Clk_in; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_out_Ena_out; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_out_Clk_out; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_ctr_puf_in_valid; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_ctr_puf_in_ready; // @[PUF_Top.scala 39:35]
  wire [209:0] M_PUF_Core_io_ctr_puf_data_in; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_ctr_puf_out_valid; // @[PUF_Top.scala 39:35]
  wire  M_PUF_Core_io_clk_Clk; // @[PUF_Top.scala 39:35]
  wire  M_read_data_clock; // @[PUF_Top.scala 40:35]
  wire  M_read_data_reset; // @[PUF_Top.scala 40:35]
  wire  M_read_data_io_ena; // @[PUF_Top.scala 40:35]
  wire  M_read_data_io_channel; // @[PUF_Top.scala 40:35]
  wire [127:0] M_read_data_io_output; // @[PUF_Top.scala 40:35]
  wire  the_clock_M_Clk_Divider_clock; // @[Clk_Divider2.scala 21:35]
  wire  the_clock_M_Clk_Divider_reset; // @[Clk_Divider2.scala 21:35]
  wire  the_clock_M_Clk_Divider_io_clk_out; // @[Clk_Divider2.scala 21:35]
  wire  the_clock_reverse = the_clock_M_Clk_Divider_io_clk_out ? 1'h0 : 1'h1; // @[PUF_Top.scala 44:72]
  reg  M_read_data_io_ena_REG; // @[PUF_Top.scala 51:40]
  reg  the_ena_in; // @[PUF_Top.scala 54:40]
  reg  io_out_Data_in_REG; // @[PUF_Top.scala 58:40]
  reg  io_out_Ena_out_REG; // @[PUF_Top.scala 60:40]
  reg  io_out_Clk_in_REG; // @[PUF_Top.scala 61:40]
  reg  io_out_Clk_out_REG; // @[PUF_Top.scala 62:40]
  reg  io_out_Clk_REG; // @[PUF_Top.scala 65:40]
  reg  io_out_WL_Enable_REG; // @[PUF_Top.scala 66:40]
  reg  io_out_Write_Ena_REG; // @[PUF_Top.scala 67:40]
  puf_core M_PUF_Core ( // @[PUF_Top.scala 39:35]
    .clock(M_PUF_Core_clock),
    .reset(M_PUF_Core_reset),
    .io_out_Data_in(M_PUF_Core_io_out_Data_in),
    .io_out_Ena_in(M_PUF_Core_io_out_Ena_in),
    .io_out_Clk_in(M_PUF_Core_io_out_Clk_in),
    .io_out_Ena_out(M_PUF_Core_io_out_Ena_out),
    .io_out_Clk_out(M_PUF_Core_io_out_Clk_out),
    .io_ctr_puf_in_valid(M_PUF_Core_io_ctr_puf_in_valid),
    .io_ctr_puf_in_ready(M_PUF_Core_io_ctr_puf_in_ready),
    .io_ctr_puf_data_in(M_PUF_Core_io_ctr_puf_data_in),
    .io_ctr_puf_out_valid(M_PUF_Core_io_ctr_puf_out_valid),
    .io_clk_Clk(M_PUF_Core_io_clk_Clk)
  );
  read_data M_read_data ( // @[PUF_Top.scala 40:35]
    .clock(M_read_data_clock),
    .reset(M_read_data_reset),
    .io_ena(M_read_data_io_ena),
    .io_channel(M_read_data_io_channel),
    .io_output(M_read_data_io_output)
  );
  Clk_Divider2 the_clock_M_Clk_Divider ( // @[Clk_Divider2.scala 21:35]
    .clock(the_clock_M_Clk_Divider_clock),
    .reset(the_clock_M_Clk_Divider_reset),
    .io_clk_out(the_clock_M_Clk_Divider_io_clk_out)
  );
  assign io_out_Data_in = io_out_Data_in_REG; // @[PUF_Top.scala 58:29]
  assign io_out_Ena_in = the_ena_in; // @[PUF_Top.scala 59:29]
  assign io_out_Clk_in = io_out_Clk_in_REG; // @[PUF_Top.scala 61:29]
  assign io_out_Ena_out = io_out_Ena_out_REG; // @[PUF_Top.scala 60:29]
  assign io_out_Clk_out = io_out_Clk_out_REG; // @[PUF_Top.scala 62:29]
  assign io_out_Clk = io_out_Clk_REG; // @[PUF_Top.scala 65:29]
  assign io_out_WL_Enable = io_out_WL_Enable_REG; // @[PUF_Top.scala 66:29]
  assign io_out_Write_Ena = io_out_Write_Ena_REG; // @[PUF_Top.scala 67:29]
  assign io_ctr_puf_in_ready = M_PUF_Core_io_ctr_puf_in_ready; // @[PUF_Top.scala 70:37]
  assign io_ctr_puf_out_valid = M_PUF_Core_io_ctr_puf_out_valid; // @[PUF_Top.scala 73:37]
  assign io_ctr_puf_data_out = M_read_data_io_output; // @[PUF_Top.scala 75:37]
  assign M_PUF_Core_clock = clock;
  assign M_PUF_Core_reset = reset;
  assign M_PUF_Core_io_ctr_puf_in_valid = io_ctr_puf_in_valid; // @[PUF_Top.scala 69:37]
  assign M_PUF_Core_io_ctr_puf_data_in = io_ctr_puf_data_in; // @[PUF_Top.scala 71:37]
  assign M_PUF_Core_io_clk_Clk = the_clock_M_Clk_Divider_io_clk_out ? 1'h0 : 1'h1; // @[PUF_Top.scala 44:72]
  assign M_read_data_clock = the_clock_M_Clk_Divider_io_clk_out; // @[PUF_Top.scala 50:29]
  assign M_read_data_reset = reset;
  assign M_read_data_io_ena = M_read_data_io_ena_REG; // @[PUF_Top.scala 51:29]
  assign M_read_data_io_channel = io_out_Data_out; // @[PUF_Top.scala 52:29]
  assign the_clock_M_Clk_Divider_clock = clock;
  assign the_clock_M_Clk_Divider_reset = reset;
  always @(posedge clock) begin
    M_read_data_io_ena_REG <= M_PUF_Core_io_out_Ena_out; // @[PUF_Top.scala 51:40]
    the_ena_in <= M_PUF_Core_io_out_Ena_in; // @[PUF_Top.scala 54:40]
    io_out_Data_in_REG <= M_PUF_Core_io_out_Data_in; // @[PUF_Top.scala 58:40]
    io_out_Ena_out_REG <= M_PUF_Core_io_out_Ena_out; // @[PUF_Top.scala 60:40]
    io_out_Clk_in_REG <= M_PUF_Core_io_out_Clk_in & the_clock_M_Clk_Divider_io_clk_out; // @[PUF_Top.scala 61:66]
    io_out_Clk_out_REG <= M_PUF_Core_io_out_Clk_out & the_clock_reverse; // @[PUF_Top.scala 62:67]
    io_out_Clk_REG <= the_ena_in; // @[PUF_Top.scala 65:40]
    io_out_WL_Enable_REG <= io_ctr_puf_wl_ena & the_ena_in; // @[PUF_Top.scala 55:36]
    io_out_Write_Ena_REG <= io_ctr_puf_write_ena & the_ena_in; // @[PUF_Top.scala 56:36]
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  M_read_data_io_ena_REG = _RAND_0[0:0];
  _RAND_1 = {1{`RANDOM}};
  the_ena_in = _RAND_1[0:0];
  _RAND_2 = {1{`RANDOM}};
  io_out_Data_in_REG = _RAND_2[0:0];
  _RAND_3 = {1{`RANDOM}};
  io_out_Ena_out_REG = _RAND_3[0:0];
  _RAND_4 = {1{`RANDOM}};
  io_out_Clk_in_REG = _RAND_4[0:0];
  _RAND_5 = {1{`RANDOM}};
  io_out_Clk_out_REG = _RAND_5[0:0];
  _RAND_6 = {1{`RANDOM}};
  io_out_Clk_REG = _RAND_6[0:0];
  _RAND_7 = {1{`RANDOM}};
  io_out_WL_Enable_REG = _RAND_7[0:0];
  _RAND_8 = {1{`RANDOM}};
  io_out_Write_Ena_REG = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module puf_top(
  input          clock,
  input          reset,
  output         io_out_Data_in,
  output         io_out_Ena_in,
  output         io_out_Clk_in,
  input          io_out_Data_out,
  output         io_out_Ena_out,
  output         io_out_Clk_out,
  output         io_out_Clk,
  output         io_out_WL_Enable,
  output         io_out_Write_Ena,
  input          io_ctr_puf_in_valid,
  output         io_ctr_puf_in_ready,
  input  [209:0] io_ctr_puf_data_in,
  output         io_ctr_puf_out_valid,
  output [127:0] io_ctr_puf_data_out,
  input          io_ctr_puf_wl_ena,
  input          io_ctr_puf_write_ena
);
  wire  M_PUF_SubTop_clock; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_reset; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Data_in; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Ena_in; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Clk_in; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Data_out; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Ena_out; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Clk_out; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Clk; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_WL_Enable; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_out_Write_Ena; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_ctr_puf_in_valid; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_ctr_puf_in_ready; // @[PUF_Top.scala 19:35]
  wire [209:0] M_PUF_SubTop_io_ctr_puf_data_in; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_ctr_puf_out_valid; // @[PUF_Top.scala 19:35]
  wire [127:0] M_PUF_SubTop_io_ctr_puf_data_out; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_ctr_puf_wl_ena; // @[PUF_Top.scala 19:35]
  wire  M_PUF_SubTop_io_ctr_puf_write_ena; // @[PUF_Top.scala 19:35]
  wire  M_Clk_Divider_clk; // @[PUF_Top.scala 20:35]
  wire  M_Clk_Divider_rst_p; // @[PUF_Top.scala 20:35]
  wire  M_Clk_Divider_clk_div; // @[PUF_Top.scala 20:35]
  puf_subtop M_PUF_SubTop ( // @[PUF_Top.scala 19:35]
    .clock(M_PUF_SubTop_clock),
    .reset(M_PUF_SubTop_reset),
    .io_out_Data_in(M_PUF_SubTop_io_out_Data_in),
    .io_out_Ena_in(M_PUF_SubTop_io_out_Ena_in),
    .io_out_Clk_in(M_PUF_SubTop_io_out_Clk_in),
    .io_out_Data_out(M_PUF_SubTop_io_out_Data_out),
    .io_out_Ena_out(M_PUF_SubTop_io_out_Ena_out),
    .io_out_Clk_out(M_PUF_SubTop_io_out_Clk_out),
    .io_out_Clk(M_PUF_SubTop_io_out_Clk),
    .io_out_WL_Enable(M_PUF_SubTop_io_out_WL_Enable),
    .io_out_Write_Ena(M_PUF_SubTop_io_out_Write_Ena),
    .io_ctr_puf_in_valid(M_PUF_SubTop_io_ctr_puf_in_valid),
    .io_ctr_puf_in_ready(M_PUF_SubTop_io_ctr_puf_in_ready),
    .io_ctr_puf_data_in(M_PUF_SubTop_io_ctr_puf_data_in),
    .io_ctr_puf_out_valid(M_PUF_SubTop_io_ctr_puf_out_valid),
    .io_ctr_puf_data_out(M_PUF_SubTop_io_ctr_puf_data_out),
    .io_ctr_puf_wl_ena(M_PUF_SubTop_io_ctr_puf_wl_ena),
    .io_ctr_puf_write_ena(M_PUF_SubTop_io_ctr_puf_write_ena)
  );
  clk_divider #(.NUM_DIV(100), .CNT_LEN(8)) M_Clk_Divider ( // @[PUF_Top.scala 20:35]
    .clk(M_Clk_Divider_clk),
    .rst_p(M_Clk_Divider_rst_p),
    .clk_div(M_Clk_Divider_clk_div)
  );
  assign io_out_Data_in = M_PUF_SubTop_io_out_Data_in; // @[PUF_Top.scala 28:29]
  assign io_out_Ena_in = M_PUF_SubTop_io_out_Ena_in; // @[PUF_Top.scala 28:29]
  assign io_out_Clk_in = M_PUF_SubTop_io_out_Clk_in; // @[PUF_Top.scala 28:29]
  assign io_out_Ena_out = M_PUF_SubTop_io_out_Ena_out; // @[PUF_Top.scala 28:29]
  assign io_out_Clk_out = M_PUF_SubTop_io_out_Clk_out; // @[PUF_Top.scala 28:29]
  assign io_out_Clk = M_PUF_SubTop_io_out_Clk; // @[PUF_Top.scala 28:29]
  assign io_out_WL_Enable = M_PUF_SubTop_io_out_WL_Enable; // @[PUF_Top.scala 28:29]
  assign io_out_Write_Ena = M_PUF_SubTop_io_out_Write_Ena; // @[PUF_Top.scala 28:29]
  assign io_ctr_puf_in_ready = M_PUF_SubTop_io_ctr_puf_in_ready; // @[PUF_Top.scala 29:29]
  assign io_ctr_puf_out_valid = M_PUF_SubTop_io_ctr_puf_out_valid; // @[PUF_Top.scala 29:29]
  assign io_ctr_puf_data_out = M_PUF_SubTop_io_ctr_puf_data_out; // @[PUF_Top.scala 29:29]
  assign M_PUF_SubTop_clock = M_Clk_Divider_clk_div; // @[PUF_Top.scala 22:33 PUF_Top.scala 25:29]
  assign M_PUF_SubTop_reset = reset;
  assign M_PUF_SubTop_io_out_Data_out = io_out_Data_out; // @[PUF_Top.scala 28:29]
  assign M_PUF_SubTop_io_ctr_puf_in_valid = io_ctr_puf_in_valid; // @[PUF_Top.scala 29:29]
  assign M_PUF_SubTop_io_ctr_puf_data_in = io_ctr_puf_data_in; // @[PUF_Top.scala 29:29]
  assign M_PUF_SubTop_io_ctr_puf_wl_ena = io_ctr_puf_wl_ena; // @[PUF_Top.scala 29:29]
  assign M_PUF_SubTop_io_ctr_puf_write_ena = io_ctr_puf_write_ena; // @[PUF_Top.scala 29:29]
  assign M_Clk_Divider_clk = clock; // @[PUF_Top.scala 23:29]
  assign M_Clk_Divider_rst_p = reset; // @[PUF_Top.scala 24:39]
endmodule
module control(
  input          clock,
  input          reset,
  input          io_uart_tx_ready,
  output         io_uart_tx_valid,
  output [7:0]   io_uart_tx_data,
  input  [7:0]   io_uart_rx_data,
  input          io_uart_rx_valid,
  output         io_uart_rx_ready,
  output         io_puf_in_valid,
  input          io_puf_in_ready,
  output [209:0] io_puf_data_in,
  input          io_puf_out_valid,
  input  [127:0] io_puf_data_out,
  output         io_puf_wl_ena,
  output         io_puf_write_ena,
  output [7:0]   io_led
);
`ifdef RANDOMIZE_REG_INIT
  reg [31:0] _RAND_0;
  reg [31:0] _RAND_1;
  reg [31:0] _RAND_2;
  reg [31:0] _RAND_3;
  reg [31:0] _RAND_4;
  reg [31:0] _RAND_5;
  reg [31:0] _RAND_6;
  reg [31:0] _RAND_7;
  reg [31:0] _RAND_8;
  reg [31:0] _RAND_9;
  reg [31:0] _RAND_10;
  reg [31:0] _RAND_11;
  reg [31:0] _RAND_12;
  reg [31:0] _RAND_13;
  reg [31:0] _RAND_14;
  reg [31:0] _RAND_15;
  reg [31:0] _RAND_16;
  reg [31:0] _RAND_17;
  reg [31:0] _RAND_18;
  reg [31:0] _RAND_19;
  reg [31:0] _RAND_20;
  reg [31:0] _RAND_21;
  reg [31:0] _RAND_22;
  reg [31:0] _RAND_23;
  reg [31:0] _RAND_24;
  reg [31:0] _RAND_25;
  reg [31:0] _RAND_26;
  reg [31:0] _RAND_27;
  reg [31:0] _RAND_28;
  reg [31:0] _RAND_29;
  reg [31:0] _RAND_30;
  reg [31:0] _RAND_31;
  reg [31:0] _RAND_32;
  reg [31:0] _RAND_33;
  reg [31:0] _RAND_34;
  reg [31:0] _RAND_35;
  reg [31:0] _RAND_36;
  reg [31:0] _RAND_37;
  reg [31:0] _RAND_38;
  reg [31:0] _RAND_39;
  reg [31:0] _RAND_40;
  reg [31:0] _RAND_41;
  reg [31:0] _RAND_42;
  reg [31:0] _RAND_43;
  reg [31:0] _RAND_44;
  reg [31:0] _RAND_45;
  reg [31:0] _RAND_46;
`endif // RANDOMIZE_REG_INIT
  reg [7:0] data_control; // @[control.scala 45:40]
  reg [7:0] data_stimulus_0; // @[control.scala 46:40]
  reg [7:0] data_stimulus_1; // @[control.scala 46:40]
  reg [7:0] data_stimulus_2; // @[control.scala 46:40]
  reg [7:0] data_stimulus_3; // @[control.scala 46:40]
  reg [7:0] data_stimulus_4; // @[control.scala 46:40]
  reg [7:0] data_stimulus_5; // @[control.scala 46:40]
  reg [7:0] data_stimulus_6; // @[control.scala 46:40]
  reg [7:0] data_stimulus_7; // @[control.scala 46:40]
  reg [7:0] data_stimulus_8; // @[control.scala 46:40]
  reg [7:0] data_stimulus_9; // @[control.scala 46:40]
  reg [7:0] data_stimulus_10; // @[control.scala 46:40]
  reg [7:0] data_stimulus_11; // @[control.scala 46:40]
  reg [7:0] data_stimulus_12; // @[control.scala 46:40]
  reg [7:0] data_stimulus_13; // @[control.scala 46:40]
  reg [7:0] data_stimulus_14; // @[control.scala 46:40]
  reg [7:0] data_stimulus_15; // @[control.scala 46:40]
  reg [7:0] data_stimulus_16; // @[control.scala 46:40]
  reg [7:0] data_stimulus_17; // @[control.scala 46:40]
  reg [7:0] data_stimulus_18; // @[control.scala 46:40]
  reg [7:0] data_stimulus_19; // @[control.scala 46:40]
  reg [7:0] data_stimulus_20; // @[control.scala 46:40]
  reg [7:0] data_stimulus_21; // @[control.scala 46:40]
  reg [7:0] data_stimulus_22; // @[control.scala 46:40]
  reg [7:0] data_stimulus_23; // @[control.scala 46:40]
  reg [7:0] data_stimulus_24; // @[control.scala 46:40]
  reg [7:0] data_stimulus_25; // @[control.scala 46:40]
  reg [7:0] data_stimulus_26; // @[control.scala 46:40]
  reg [7:0] data_output_0; // @[control.scala 47:40]
  reg [7:0] data_output_1; // @[control.scala 47:40]
  reg [7:0] data_output_2; // @[control.scala 47:40]
  reg [7:0] data_output_3; // @[control.scala 47:40]
  reg [7:0] data_output_4; // @[control.scala 47:40]
  reg [7:0] data_output_5; // @[control.scala 47:40]
  reg [7:0] data_output_6; // @[control.scala 47:40]
  reg [7:0] data_output_7; // @[control.scala 47:40]
  reg [7:0] data_output_8; // @[control.scala 47:40]
  reg [7:0] data_output_9; // @[control.scala 47:40]
  reg [7:0] data_output_10; // @[control.scala 47:40]
  reg [7:0] data_output_11; // @[control.scala 47:40]
  reg [7:0] data_output_12; // @[control.scala 47:40]
  reg [7:0] data_output_13; // @[control.scala 47:40]
  reg [7:0] data_output_14; // @[control.scala 47:40]
  reg [7:0] data_output_15; // @[control.scala 47:40]
  reg [9:0] cnt_input; // @[control.scala 52:36]
  reg [9:0] cnt_output; // @[control.scala 53:36]
  reg [2:0] stateReg; // @[control.scala 63:32]
  wire  trigger_receive = io_uart_rx_valid & io_uart_rx_data == 8'h53; // @[control.scala 73:28]
  wire  trigger_pufin = cnt_input == 10'h1c; // @[control.scala 79:21]
  wire [4:0] _T_4 = 5'h10 - 5'h1; // @[control.scala 97:40]
  wire [9:0] _GEN_187 = {{5'd0}, _T_4}; // @[control.scala 97:22]
  wire  trigger_done = cnt_output == _GEN_187; // @[control.scala 97:22]
  wire  _T_7 = stateReg == 3'h1; // @[control.scala 115:25]
  wire  _T_8 = stateReg == 3'h2; // @[control.scala 120:25]
  wire [2:0] _GEN_7 = io_puf_in_ready ? 3'h3 : stateReg; // @[control.scala 121:31 control.scala 122:25 control.scala 63:32]
  wire  _T_9 = stateReg == 3'h3; // @[control.scala 125:25]
  wire [2:0] _GEN_8 = io_puf_out_valid ? 3'h4 : stateReg; // @[control.scala 126:29 control.scala 127:25 control.scala 63:32]
  wire  _T_10 = stateReg == 3'h4; // @[control.scala 130:25]
  wire [2:0] _GEN_9 = trigger_done ? 3'h0 : stateReg; // @[control.scala 131:29 control.scala 132:25 control.scala 63:32]
  wire [2:0] _GEN_10 = stateReg == 3'h4 ? _GEN_9 : stateReg; // @[control.scala 130:36 control.scala 63:32]
  wire [2:0] _GEN_11 = stateReg == 3'h3 ? _GEN_8 : _GEN_10; // @[control.scala 125:38]
  wire [7:0] _GEN_15 = 5'h0 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_0; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_16 = 5'h1 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_1; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_17 = 5'h2 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_2; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_18 = 5'h3 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_3; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_19 = 5'h4 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_4; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_20 = 5'h5 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_5; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_21 = 5'h6 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_6; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_22 = 5'h7 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_7; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_23 = 5'h8 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_8; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_24 = 5'h9 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_9; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_25 = 5'ha == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_10; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_26 = 5'hb == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_11; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_27 = 5'hc == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_12; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_28 = 5'hd == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_13; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_29 = 5'he == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_14; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_30 = 5'hf == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_15; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_31 = 5'h10 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_16; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_32 = 5'h11 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_17; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_33 = 5'h12 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_18; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_34 = 5'h13 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_19; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_35 = 5'h14 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_20; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_36 = 5'h15 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_21; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_37 = 5'h16 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_22; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_38 = 5'h17 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_23; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_39 = 5'h18 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_24; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_40 = 5'h19 == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_25; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_41 = 5'h1a == cnt_input[4:0] ? io_uart_rx_data : data_stimulus_26; // @[control.scala 148:49 control.scala 148:49 control.scala 46:40]
  wire [7:0] _GEN_42 = cnt_input == 10'h1b ? io_uart_rx_data : data_control; // @[control.scala 150:57 control.scala 151:33 control.scala 45:40]
  wire [9:0] _cnt_input_T_1 = cnt_input + 10'h1; // @[control.scala 154:59]
  wire [47:0] io_puf_data_in_lo_lo = {data_stimulus_5,data_stimulus_4,data_stimulus_3,data_stimulus_2,data_stimulus_1,
    data_stimulus_0}; // @[control.scala 165:43]
  wire [103:0] io_puf_data_in_lo = {data_stimulus_12,data_stimulus_11,data_stimulus_10,data_stimulus_9,data_stimulus_8,
    data_stimulus_7,data_stimulus_6,io_puf_data_in_lo_lo}; // @[control.scala 165:43]
  wire [55:0] io_puf_data_in_hi_lo = {data_stimulus_19,data_stimulus_18,data_stimulus_17,data_stimulus_16,
    data_stimulus_15,data_stimulus_14,data_stimulus_13}; // @[control.scala 165:43]
  wire [215:0] _io_puf_data_in_T = {data_stimulus_26,data_stimulus_25,data_stimulus_24,data_stimulus_23,data_stimulus_22
    ,data_stimulus_21,data_stimulus_20,io_puf_data_in_hi_lo,io_puf_data_in_lo}; // @[control.scala 165:43]
  wire [215:0] _GEN_130 = _T_8 ? _io_puf_data_in_T : 216'h0; // @[control.scala 161:32 control.scala 165:25 control.scala 168:25]
  wire [7:0] _GEN_167 = 4'h1 == cnt_output[3:0] ? data_output_1 : data_output_0; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_168 = 4'h2 == cnt_output[3:0] ? data_output_2 : _GEN_167; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_169 = 4'h3 == cnt_output[3:0] ? data_output_3 : _GEN_168; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_170 = 4'h4 == cnt_output[3:0] ? data_output_4 : _GEN_169; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_171 = 4'h5 == cnt_output[3:0] ? data_output_5 : _GEN_170; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_172 = 4'h6 == cnt_output[3:0] ? data_output_6 : _GEN_171; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_173 = 4'h7 == cnt_output[3:0] ? data_output_7 : _GEN_172; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_174 = 4'h8 == cnt_output[3:0] ? data_output_8 : _GEN_173; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_175 = 4'h9 == cnt_output[3:0] ? data_output_9 : _GEN_174; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_176 = 4'ha == cnt_output[3:0] ? data_output_10 : _GEN_175; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_177 = 4'hb == cnt_output[3:0] ? data_output_11 : _GEN_176; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_178 = 4'hc == cnt_output[3:0] ? data_output_12 : _GEN_177; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_179 = 4'hd == cnt_output[3:0] ? data_output_13 : _GEN_178; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_180 = 4'he == cnt_output[3:0] ? data_output_14 : _GEN_179; // @[control.scala 208:29 control.scala 208:29]
  wire [7:0] _GEN_181 = 4'hf == cnt_output[3:0] ? data_output_15 : _GEN_180; // @[control.scala 208:29 control.scala 208:29]
  wire [9:0] _cnt_output_T_1 = cnt_output + 10'h1; // @[control.scala 209:44]
  wire [7:0] _GEN_182 = io_uart_tx_ready ? _GEN_181 : 8'h0; // @[control.scala 207:33 control.scala 208:29 control.scala 211:29]
  assign io_uart_tx_valid = stateReg == 3'h4; // @[control.scala 205:20]
  assign io_uart_tx_data = _T_10 ? _GEN_182 : 8'h0; // @[control.scala 205:31 control.scala 214:29]
  assign io_uart_rx_ready = 1'h1; // @[control.scala 143:25]
  assign io_puf_in_valid = stateReg == 3'h2; // @[control.scala 161:20]
  assign io_puf_data_in = _GEN_130[209:0];
  assign io_puf_wl_ena = _T_9 & data_control[3:0] == 4'hf; // @[control.scala 177:33 control.scala 182:33 control.scala 201:29]
  assign io_puf_write_ena = _T_9 & data_control[7:4] == 4'hf; // @[control.scala 177:33 control.scala 183:33 control.scala 202:29]
  assign io_led = data_control; // @[control.scala 50:29]
  always @(posedge clock) begin
    if (reset) begin // @[control.scala 45:40]
      data_control <= 8'h0; // @[control.scala 45:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (!(cnt_input < 10'h1b)) begin // @[control.scala 147:50]
          data_control <= _GEN_42;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_0 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_0 <= _GEN_15;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_1 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_1 <= _GEN_16;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_2 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_2 <= _GEN_17;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_3 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_3 <= _GEN_18;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_4 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_4 <= _GEN_19;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_5 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_5 <= _GEN_20;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_6 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_6 <= _GEN_21;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_7 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_7 <= _GEN_22;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_8 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_8 <= _GEN_23;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_9 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_9 <= _GEN_24;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_10 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_10 <= _GEN_25;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_11 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_11 <= _GEN_26;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_12 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_12 <= _GEN_27;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_13 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_13 <= _GEN_28;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_14 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_14 <= _GEN_29;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_15 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_15 <= _GEN_30;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_16 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_16 <= _GEN_31;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_17 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_17 <= _GEN_32;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_18 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_18 <= _GEN_33;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_19 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_19 <= _GEN_34;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_20 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_20 <= _GEN_35;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_21 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_21 <= _GEN_36;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_22 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_22 <= _GEN_37;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_23 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_23 <= _GEN_38;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_24 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_24 <= _GEN_39;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_25 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_25 <= _GEN_40;
        end
      end
    end
    if (reset) begin // @[control.scala 46:40]
      data_stimulus_26 <= 8'h0; // @[control.scala 46:40]
    end else if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        if (cnt_input < 10'h1b) begin // @[control.scala 147:50]
          data_stimulus_26 <= _GEN_41;
        end
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_0 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_0 <= io_puf_data_out[7:0]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_1 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_1 <= io_puf_data_out[15:8]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_2 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_2 <= io_puf_data_out[23:16]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_3 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_3 <= io_puf_data_out[31:24]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_4 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_4 <= io_puf_data_out[39:32]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_5 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_5 <= io_puf_data_out[47:40]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_6 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_6 <= io_puf_data_out[55:48]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_7 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_7 <= io_puf_data_out[63:56]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_8 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_8 <= io_puf_data_out[71:64]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_9 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_9 <= io_puf_data_out[79:72]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_10 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_10 <= io_puf_data_out[87:80]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_11 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_11 <= io_puf_data_out[95:88]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_12 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_12 <= io_puf_data_out[103:96]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_13 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_13 <= io_puf_data_out[111:104]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_14 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_14 <= io_puf_data_out[119:112]; // @[control.scala 187:32]
      end
    end
    if (reset) begin // @[control.scala 47:40]
      data_output_15 <= 8'h0; // @[control.scala 47:40]
    end else if (_T_9) begin // @[control.scala 177:33]
      if (io_puf_out_valid) begin // @[control.scala 185:33]
        data_output_15 <= io_puf_data_out[127:120]; // @[control.scala 187:32]
      end
    end
    if (_T_7) begin // @[control.scala 145:33]
      if (io_uart_rx_valid) begin // @[control.scala 146:33]
        cnt_input <= _cnt_input_T_1; // @[control.scala 154:45]
      end
    end else begin
      cnt_input <= 10'h0; // @[control.scala 157:21]
    end
    if (_T_10) begin // @[control.scala 205:31]
      if (io_uart_tx_ready) begin // @[control.scala 207:33]
        cnt_output <= _cnt_output_T_1; // @[control.scala 209:29]
      end
    end else begin
      cnt_output <= 10'h0; // @[control.scala 216:29]
    end
    if (reset) begin // @[control.scala 63:32]
      stateReg <= 3'h0; // @[control.scala 63:32]
    end else if (stateReg == 3'h0) begin // @[control.scala 110:31]
      if (trigger_receive) begin // @[control.scala 111:32]
        stateReg <= 3'h1; // @[control.scala 112:25]
      end
    end else if (stateReg == 3'h1) begin // @[control.scala 115:38]
      if (trigger_pufin) begin // @[control.scala 116:30]
        stateReg <= 3'h2; // @[control.scala 117:25]
      end
    end else if (stateReg == 3'h2) begin // @[control.scala 120:37]
      stateReg <= _GEN_7;
    end else begin
      stateReg <= _GEN_11;
    end
  end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
  `ifdef RANDOMIZE
    `ifdef INIT_RANDOM
      `INIT_RANDOM
    `endif
    `ifndef VERILATOR
      `ifdef RANDOMIZE_DELAY
        #`RANDOMIZE_DELAY begin end
      `else
        #0.002 begin end
      `endif
    `endif
`ifdef RANDOMIZE_REG_INIT
  _RAND_0 = {1{`RANDOM}};
  data_control = _RAND_0[7:0];
  _RAND_1 = {1{`RANDOM}};
  data_stimulus_0 = _RAND_1[7:0];
  _RAND_2 = {1{`RANDOM}};
  data_stimulus_1 = _RAND_2[7:0];
  _RAND_3 = {1{`RANDOM}};
  data_stimulus_2 = _RAND_3[7:0];
  _RAND_4 = {1{`RANDOM}};
  data_stimulus_3 = _RAND_4[7:0];
  _RAND_5 = {1{`RANDOM}};
  data_stimulus_4 = _RAND_5[7:0];
  _RAND_6 = {1{`RANDOM}};
  data_stimulus_5 = _RAND_6[7:0];
  _RAND_7 = {1{`RANDOM}};
  data_stimulus_6 = _RAND_7[7:0];
  _RAND_8 = {1{`RANDOM}};
  data_stimulus_7 = _RAND_8[7:0];
  _RAND_9 = {1{`RANDOM}};
  data_stimulus_8 = _RAND_9[7:0];
  _RAND_10 = {1{`RANDOM}};
  data_stimulus_9 = _RAND_10[7:0];
  _RAND_11 = {1{`RANDOM}};
  data_stimulus_10 = _RAND_11[7:0];
  _RAND_12 = {1{`RANDOM}};
  data_stimulus_11 = _RAND_12[7:0];
  _RAND_13 = {1{`RANDOM}};
  data_stimulus_12 = _RAND_13[7:0];
  _RAND_14 = {1{`RANDOM}};
  data_stimulus_13 = _RAND_14[7:0];
  _RAND_15 = {1{`RANDOM}};
  data_stimulus_14 = _RAND_15[7:0];
  _RAND_16 = {1{`RANDOM}};
  data_stimulus_15 = _RAND_16[7:0];
  _RAND_17 = {1{`RANDOM}};
  data_stimulus_16 = _RAND_17[7:0];
  _RAND_18 = {1{`RANDOM}};
  data_stimulus_17 = _RAND_18[7:0];
  _RAND_19 = {1{`RANDOM}};
  data_stimulus_18 = _RAND_19[7:0];
  _RAND_20 = {1{`RANDOM}};
  data_stimulus_19 = _RAND_20[7:0];
  _RAND_21 = {1{`RANDOM}};
  data_stimulus_20 = _RAND_21[7:0];
  _RAND_22 = {1{`RANDOM}};
  data_stimulus_21 = _RAND_22[7:0];
  _RAND_23 = {1{`RANDOM}};
  data_stimulus_22 = _RAND_23[7:0];
  _RAND_24 = {1{`RANDOM}};
  data_stimulus_23 = _RAND_24[7:0];
  _RAND_25 = {1{`RANDOM}};
  data_stimulus_24 = _RAND_25[7:0];
  _RAND_26 = {1{`RANDOM}};
  data_stimulus_25 = _RAND_26[7:0];
  _RAND_27 = {1{`RANDOM}};
  data_stimulus_26 = _RAND_27[7:0];
  _RAND_28 = {1{`RANDOM}};
  data_output_0 = _RAND_28[7:0];
  _RAND_29 = {1{`RANDOM}};
  data_output_1 = _RAND_29[7:0];
  _RAND_30 = {1{`RANDOM}};
  data_output_2 = _RAND_30[7:0];
  _RAND_31 = {1{`RANDOM}};
  data_output_3 = _RAND_31[7:0];
  _RAND_32 = {1{`RANDOM}};
  data_output_4 = _RAND_32[7:0];
  _RAND_33 = {1{`RANDOM}};
  data_output_5 = _RAND_33[7:0];
  _RAND_34 = {1{`RANDOM}};
  data_output_6 = _RAND_34[7:0];
  _RAND_35 = {1{`RANDOM}};
  data_output_7 = _RAND_35[7:0];
  _RAND_36 = {1{`RANDOM}};
  data_output_8 = _RAND_36[7:0];
  _RAND_37 = {1{`RANDOM}};
  data_output_9 = _RAND_37[7:0];
  _RAND_38 = {1{`RANDOM}};
  data_output_10 = _RAND_38[7:0];
  _RAND_39 = {1{`RANDOM}};
  data_output_11 = _RAND_39[7:0];
  _RAND_40 = {1{`RANDOM}};
  data_output_12 = _RAND_40[7:0];
  _RAND_41 = {1{`RANDOM}};
  data_output_13 = _RAND_41[7:0];
  _RAND_42 = {1{`RANDOM}};
  data_output_14 = _RAND_42[7:0];
  _RAND_43 = {1{`RANDOM}};
  data_output_15 = _RAND_43[7:0];
  _RAND_44 = {1{`RANDOM}};
  cnt_input = _RAND_44[9:0];
  _RAND_45 = {1{`RANDOM}};
  cnt_output = _RAND_45[9:0];
  _RAND_46 = {1{`RANDOM}};
  stateReg = _RAND_46[2:0];
`endif // RANDOMIZE_REG_INIT
  `endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
module top(
  input        clock,
  input        reset,
  output [7:0] io_led_led,
  output       io_test_out,
  input        io_uart_uart_rx,
  output       io_uart_uart_tx,
  output       io_puf_out_Data_in,
  output       io_puf_out_Ena_in,
  output       io_puf_out_Clk_in,
  input        io_puf_out_Data_out,
  output       io_puf_out_Ena_out,
  output       io_puf_out_Clk_out,
  output       io_puf_out_Clk,
  output       io_puf_out_WL_Enable,
  output       io_puf_out_Write_Ena
);
  wire  M_puf_clock; // @[top.scala 19:35]
  wire  M_puf_reset; // @[top.scala 19:35]
  wire  M_puf_io_out_Data_in; // @[top.scala 19:35]
  wire  M_puf_io_out_Ena_in; // @[top.scala 19:35]
  wire  M_puf_io_out_Clk_in; // @[top.scala 19:35]
  wire  M_puf_io_out_Data_out; // @[top.scala 19:35]
  wire  M_puf_io_out_Ena_out; // @[top.scala 19:35]
  wire  M_puf_io_out_Clk_out; // @[top.scala 19:35]
  wire  M_puf_io_out_Clk; // @[top.scala 19:35]
  wire  M_puf_io_out_WL_Enable; // @[top.scala 19:35]
  wire  M_puf_io_out_Write_Ena; // @[top.scala 19:35]
  wire  M_puf_io_ctr_puf_in_valid; // @[top.scala 19:35]
  wire  M_puf_io_ctr_puf_in_ready; // @[top.scala 19:35]
  wire [209:0] M_puf_io_ctr_puf_data_in; // @[top.scala 19:35]
  wire  M_puf_io_ctr_puf_out_valid; // @[top.scala 19:35]
  wire [127:0] M_puf_io_ctr_puf_data_out; // @[top.scala 19:35]
  wire  M_puf_io_ctr_puf_wl_ena; // @[top.scala 19:35]
  wire  M_puf_io_ctr_puf_write_ena; // @[top.scala 19:35]
  wire  M_control_clock; // @[top.scala 20:35]
  wire  M_control_reset; // @[top.scala 20:35]
  wire  M_control_io_uart_tx_ready; // @[top.scala 20:35]
  wire  M_control_io_uart_tx_valid; // @[top.scala 20:35]
  wire [7:0] M_control_io_uart_tx_data; // @[top.scala 20:35]
  wire [7:0] M_control_io_uart_rx_data; // @[top.scala 20:35]
  wire  M_control_io_uart_rx_valid; // @[top.scala 20:35]
  wire  M_control_io_uart_rx_ready; // @[top.scala 20:35]
  wire  M_control_io_puf_in_valid; // @[top.scala 20:35]
  wire  M_control_io_puf_in_ready; // @[top.scala 20:35]
  wire [209:0] M_control_io_puf_data_in; // @[top.scala 20:35]
  wire  M_control_io_puf_out_valid; // @[top.scala 20:35]
  wire [127:0] M_control_io_puf_data_out; // @[top.scala 20:35]
  wire  M_control_io_puf_wl_ena; // @[top.scala 20:35]
  wire  M_control_io_puf_write_ena; // @[top.scala 20:35]
  wire [7:0] M_control_io_led; // @[top.scala 20:35]
  wire  M_uart_tx_clk; // @[top.scala 21:35]
  wire  M_uart_tx_rst_n; // @[top.scala 21:35]
  wire [7:0] M_uart_tx_tx_data; // @[top.scala 21:35]
  wire  M_uart_tx_tx_data_valid; // @[top.scala 21:35]
  wire  M_uart_tx_tx_data_ready; // @[top.scala 21:35]
  wire  M_uart_tx_tx_pin; // @[top.scala 21:35]
  wire  M_uart_rx_clk; // @[top.scala 22:35]
  wire  M_uart_rx_rst_n; // @[top.scala 22:35]
  wire  M_uart_rx_rx_data_ready; // @[top.scala 22:35]
  wire  M_uart_rx_rx_pin; // @[top.scala 22:35]
  wire [7:0] M_uart_rx_rx_data; // @[top.scala 22:35]
  wire  M_uart_rx_rx_data_valid; // @[top.scala 22:35]
  wire  M_Clk_Divider_clk; // @[top.scala 35:35]
  wire  M_Clk_Divider_rst_p; // @[top.scala 35:35]
  wire  M_Clk_Divider_clk_div; // @[top.scala 35:35]
  puf_top M_puf ( // @[top.scala 19:35]
    .clock(M_puf_clock),
    .reset(M_puf_reset),
    .io_out_Data_in(M_puf_io_out_Data_in),
    .io_out_Ena_in(M_puf_io_out_Ena_in),
    .io_out_Clk_in(M_puf_io_out_Clk_in),
    .io_out_Data_out(M_puf_io_out_Data_out),
    .io_out_Ena_out(M_puf_io_out_Ena_out),
    .io_out_Clk_out(M_puf_io_out_Clk_out),
    .io_out_Clk(M_puf_io_out_Clk),
    .io_out_WL_Enable(M_puf_io_out_WL_Enable),
    .io_out_Write_Ena(M_puf_io_out_Write_Ena),
    .io_ctr_puf_in_valid(M_puf_io_ctr_puf_in_valid),
    .io_ctr_puf_in_ready(M_puf_io_ctr_puf_in_ready),
    .io_ctr_puf_data_in(M_puf_io_ctr_puf_data_in),
    .io_ctr_puf_out_valid(M_puf_io_ctr_puf_out_valid),
    .io_ctr_puf_data_out(M_puf_io_ctr_puf_data_out),
    .io_ctr_puf_wl_ena(M_puf_io_ctr_puf_wl_ena),
    .io_ctr_puf_write_ena(M_puf_io_ctr_puf_write_ena)
  );
  control M_control ( // @[top.scala 20:35]
    .clock(M_control_clock),
    .reset(M_control_reset),
    .io_uart_tx_ready(M_control_io_uart_tx_ready),
    .io_uart_tx_valid(M_control_io_uart_tx_valid),
    .io_uart_tx_data(M_control_io_uart_tx_data),
    .io_uart_rx_data(M_control_io_uart_rx_data),
    .io_uart_rx_valid(M_control_io_uart_rx_valid),
    .io_uart_rx_ready(M_control_io_uart_rx_ready),
    .io_puf_in_valid(M_control_io_puf_in_valid),
    .io_puf_in_ready(M_control_io_puf_in_ready),
    .io_puf_data_in(M_control_io_puf_data_in),
    .io_puf_out_valid(M_control_io_puf_out_valid),
    .io_puf_data_out(M_control_io_puf_data_out),
    .io_puf_wl_ena(M_control_io_puf_wl_ena),
    .io_puf_write_ena(M_control_io_puf_write_ena),
    .io_led(M_control_io_led)
  );
  uart_tx #(.CLK_FRE(100), .BAUD_RATE(115200)) M_uart_tx ( // @[top.scala 21:35]
    .clk(M_uart_tx_clk),
    .rst_n(M_uart_tx_rst_n),
    .tx_data(M_uart_tx_tx_data),
    .tx_data_valid(M_uart_tx_tx_data_valid),
    .tx_data_ready(M_uart_tx_tx_data_ready),
    .tx_pin(M_uart_tx_tx_pin)
  );
  uart_rx #(.CLK_FRE(100), .BAUD_RATE(115200)) M_uart_rx ( // @[top.scala 22:35]
    .clk(M_uart_rx_clk),
    .rst_n(M_uart_rx_rst_n),
    .rx_data_ready(M_uart_rx_rx_data_ready),
    .rx_pin(M_uart_rx_rx_pin),
    .rx_data(M_uart_rx_rx_data),
    .rx_data_valid(M_uart_rx_rx_data_valid)
  );
  clk_divider #(.NUM_DIV(100), .CNT_LEN(8)) M_Clk_Divider ( // @[top.scala 35:35]
    .clk(M_Clk_Divider_clk),
    .rst_p(M_Clk_Divider_rst_p),
    .clk_div(M_Clk_Divider_clk_div)
  );
  assign io_led_led = M_control_io_led; // @[top.scala 34:25]
  assign io_test_out = M_Clk_Divider_clk_div; // @[top.scala 38:58]
  assign io_uart_uart_tx = M_uart_tx_tx_pin; // @[top.scala 54:33]
  assign io_puf_out_Data_in = M_puf_io_out_Data_in; // @[top.scala 79:33]
  assign io_puf_out_Ena_in = M_puf_io_out_Ena_in; // @[top.scala 79:33]
  assign io_puf_out_Clk_in = M_puf_io_out_Clk_in; // @[top.scala 79:33]
  assign io_puf_out_Ena_out = M_puf_io_out_Ena_out; // @[top.scala 79:33]
  assign io_puf_out_Clk_out = M_puf_io_out_Clk_out; // @[top.scala 79:33]
  assign io_puf_out_Clk = M_puf_io_out_Clk; // @[top.scala 79:33]
  assign io_puf_out_WL_Enable = M_puf_io_out_WL_Enable; // @[top.scala 79:33]
  assign io_puf_out_Write_Ena = M_puf_io_out_Write_Ena; // @[top.scala 79:33]
  assign M_puf_clock = clock;
  assign M_puf_reset = reset;
  assign M_puf_io_out_Data_out = io_puf_out_Data_out; // @[top.scala 79:33]
  assign M_puf_io_ctr_puf_in_valid = M_control_io_puf_in_valid; // @[top.scala 80:33]
  assign M_puf_io_ctr_puf_data_in = M_control_io_puf_data_in; // @[top.scala 81:33]
  assign M_puf_io_ctr_puf_wl_ena = M_control_io_puf_wl_ena; // @[top.scala 83:33]
  assign M_puf_io_ctr_puf_write_ena = M_control_io_puf_write_ena; // @[top.scala 84:33]
  assign M_control_clock = clock;
  assign M_control_reset = reset;
  assign M_control_io_uart_tx_ready = M_uart_tx_tx_data_ready; // @[top.scala 53:33]
  assign M_control_io_uart_rx_data = M_uart_rx_rx_data; // @[top.scala 69:33]
  assign M_control_io_uart_rx_valid = M_uart_rx_rx_data_valid; // @[top.scala 70:33]
  assign M_control_io_puf_in_ready = M_puf_io_ctr_puf_in_ready; // @[top.scala 86:33]
  assign M_control_io_puf_out_valid = M_puf_io_ctr_puf_out_valid; // @[top.scala 87:33]
  assign M_control_io_puf_data_out = M_puf_io_ctr_puf_data_out; // @[top.scala 88:33]
  assign M_uart_tx_clk = clock; // @[top.scala 48:33]
  assign M_uart_tx_rst_n = reset ? 1'h0 : 1'h1; // @[top.scala 25:32]
  assign M_uart_tx_tx_data = M_control_io_uart_tx_data; // @[top.scala 50:33]
  assign M_uart_tx_tx_data_valid = M_control_io_uart_tx_valid; // @[top.scala 51:33]
  assign M_uart_rx_clk = clock; // @[top.scala 64:33]
  assign M_uart_rx_rst_n = reset ? 1'h0 : 1'h1; // @[top.scala 25:32]
  assign M_uart_rx_rx_data_ready = M_control_io_uart_rx_ready; // @[top.scala 66:33]
  assign M_uart_rx_rx_pin = io_uart_uart_rx; // @[top.scala 67:33]
  assign M_Clk_Divider_clk = io_puf_out_Clk_out; // @[top.scala 36:52]
  assign M_Clk_Divider_rst_p = reset; // @[top.scala 37:39]
endmodule
